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  <div class="summary">
<a href="#nested-classes">Data Structures</a> &#124;
<a href="#enum-members">Enumerations</a>  </div>
  <div class="headertitle">
<div class="title">Data Structures<div class="ingroups"><a class="el" href="group__group__tcpwm.html">TCPWM        (Timer Counter PWM)</a> &raquo; <a class="el" href="group__group__tcpwm__pwm.html">PWM (TCPWM)</a></div></div>  </div>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__tcpwm__pwm__config__t.html">cy_stc_tcpwm_pwm_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">PWM configuration structure.  <a href="structcy__stc__tcpwm__pwm__config__t.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:ga5ba36f547c6817ce1f2a5ed6e89283ff"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga5ba36f547c6817ce1f2a5ed6e89283ff">cy_en_tcpwm_dithering_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga5ba36f547c6817ce1f2a5ed6e89283ffa184ba01f25b8da6efec3a883e558ae61">CY_TCPWM_DITHERING_DISABLE</a> = 0UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga5ba36f547c6817ce1f2a5ed6e89283ffa4a79a7cbba7cd8259444c9f22cd2734c">CY_TCPWM_DITHERING_PERIOD</a> = 1UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga5ba36f547c6817ce1f2a5ed6e89283ffa0b042dc3831108acf544ec02c5e9b93f">CY_TCPWM_DITHERING_DUTY</a> = 2UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga5ba36f547c6817ce1f2a5ed6e89283ffa38b8de205630c2679848d0fcd1950e70">CY_TCPWM_DITHERING_PERIOD_DUTY</a> = 3UL
<br />
 }<tr class="memdesc:ga5ba36f547c6817ce1f2a5ed6e89283ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCPWM Dithering.  <a href="group__group__tcpwm__data__structures__pwm.html#ga5ba36f547c6817ce1f2a5ed6e89283ff">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga5ba36f547c6817ce1f2a5ed6e89283ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3ba205fa719411684a55b9fc3ad7b79c"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga3ba205fa719411684a55b9fc3ad7b79c">cy_en_dithering_limiter_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79ca2eecdd1341a809c8219db95a13e0a984">CY_TCPWM_DITHERING_LIMITER_1</a> = 1UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79caa70075b35cc9190d26ccbdd07fe9b68d">CY_TCPWM_DITHERING_LIMITER_2</a> = 2UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79caa3d2becf221f3824633e559b2d63900b">CY_TCPWM_DITHERING_LIMITER_3</a> = 3UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79ca4c2b3761444cd8a326e0368d20bd91ee">CY_TCPWM_DITHERING_LIMITER_4</a> = 4UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79ca875edfba340d2f49fd8ccdb4a3569a96">CY_TCPWM_DITHERING_LIMITER_5</a> = 5UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79cae10ab73e45c2a8f473563be1f6583730">CY_TCPWM_DITHERING_LIMITER_6</a> = 6UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga3ba205fa719411684a55b9fc3ad7b79cab050b0e8f57b5721e29183a71dc30abc">CY_TCPWM_DITHERING_LIMITER_7</a> = 7UL
<br />
 }<tr class="memdesc:ga3ba205fa719411684a55b9fc3ad7b79c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TCPWM dithering limiter values.  <a href="group__group__tcpwm__data__structures__pwm.html#ga3ba205fa719411684a55b9fc3ad7b79c">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga3ba205fa719411684a55b9fc3ad7b79c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c9f3eeb107eae3ea2a485f9169e3759"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga8c9f3eeb107eae3ea2a485f9169e3759">cy_en_hrpwm_operating_frequency_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga8c9f3eeb107eae3ea2a485f9169e3759ad3445cddbdd169c8c23b748651c10ea6">CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ</a> = 0UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga8c9f3eeb107eae3ea2a485f9169e3759a6a2af385e701e00ffc26975e7aa52ee5">CY_TCPWM_HRPWM_FREQ_160MHZ_OR_180MHZ</a> = 1UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga8c9f3eeb107eae3ea2a485f9169e3759ad646d5983e488f45c84ff63682a09342">CY_TCPWM_HRPWM_FREQ_200MHZ_OR_240MHZ</a> = 2UL
<br />
 }<tr class="memdesc:ga8c9f3eeb107eae3ea2a485f9169e3759"><td class="mdescLeft">&#160;</td><td class="mdescRight">HRPWM Operation Frequency Selects the frequency of operation of HRPWM feature.  <a href="group__group__tcpwm__data__structures__pwm.html#ga8c9f3eeb107eae3ea2a485f9169e3759">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga8c9f3eeb107eae3ea2a485f9169e3759"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19e8127ddd17a33fe06608855cd10c4d"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga19e8127ddd17a33fe06608855cd10c4d">cy_en_kill_line_polarity_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga19e8127ddd17a33fe06608855cd10c4da4489e96d5fb2192693ccecd6b3b52251">CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW</a> = 0UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga19e8127ddd17a33fe06608855cd10c4dab544a8708f31372fd8d801493e151cf9">CY_TCPWM_LINEOUT_IS_HIGH_AND_LINECMPOUT_IS_LOW</a> = 1UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga19e8127ddd17a33fe06608855cd10c4da0a02f0fdc317e64177c0d6be7a4d5543">CY_TCPWM_LINECMPOUT_IS_HIGH_LINEOUT_IS_LOW</a> = 2UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#gga19e8127ddd17a33fe06608855cd10c4da18df07d53c406caef0834c8893814711">CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_HIGH</a> = 3UL
<br />
 }<tr class="memdesc:ga19e8127ddd17a33fe06608855cd10c4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the behavior of the PWM outputs line_out and line_out_compl_out while the TCPWM counter is disabled or stopped.  <a href="group__group__tcpwm__data__structures__pwm.html#ga19e8127ddd17a33fe06608855cd10c4d">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:ga19e8127ddd17a33fe06608855cd10c4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0adb8ee7ffc443e3ce016aec3d447c8"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__tcpwm__data__structures__pwm.html#gab0adb8ee7ffc443e3ce016aec3d447c8">cy_en_line_select_config_t</a> { <br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8a6c268b8864615e8ac0ff6086c7d5ad46">CY_TCPWM_OUTPUT_CONSTANT_0</a> = 0UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8a055953ca2ea107432c1c39cf2e60d7cc">CY_TCPWM_OUTPUT_CONSTANT_1</a> = 1UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8ab10a622c4c07bff26bd57271912f71e9">CY_TCPWM_OUTPUT_PWM_SIGNAL</a> = 2UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8a91dc81f784c9b74718d12e12902e6fe7">CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL</a> = 3UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8a324edb61b898067f6a5fe5eaa53e2271">CY_TCPWM_OUTPUT_PORT_DEFAULT</a> = 4UL, 
<br />
&#160;&#160;<a class="el" href="group__group__tcpwm__data__structures__pwm.html#ggab0adb8ee7ffc443e3ce016aec3d447c8ad1959ad6cbd6b1978e6037cf0b4ed67e">CY_TCPWM_OUTPUT_SOURCE_MOTIF</a> = 5UL
<br />
 }<tr class="memdesc:gab0adb8ee7ffc443e3ce016aec3d447c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Source for the output signal "line_out" and "line_compl_out".  <a href="group__group__tcpwm__data__structures__pwm.html#gab0adb8ee7ffc443e3ce016aec3d447c8">More...</a><br /></td></tr>
</td></tr>
<tr class="separator:gab0adb8ee7ffc443e3ce016aec3d447c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Enumeration Type Documentation</h2>
<a id="ga5ba36f547c6817ce1f2a5ed6e89283ff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5ba36f547c6817ce1f2a5ed6e89283ff">&#9670;&nbsp;</a></span>cy_en_tcpwm_dithering_t</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">enum <a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga5ba36f547c6817ce1f2a5ed6e89283ff">cy_en_tcpwm_dithering_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TCPWM Dithering. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga5ba36f547c6817ce1f2a5ed6e89283ffa184ba01f25b8da6efec3a883e558ae61"></a>CY_TCPWM_DITHERING_DISABLE&#160;</td><td class="fielddoc"><p>TCPWM dithering is disabled. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga5ba36f547c6817ce1f2a5ed6e89283ffa4a79a7cbba7cd8259444c9f22cd2734c"></a>CY_TCPWM_DITHERING_PERIOD&#160;</td><td class="fielddoc"><p>TCPWM dithering is set to period. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga5ba36f547c6817ce1f2a5ed6e89283ffa0b042dc3831108acf544ec02c5e9b93f"></a>CY_TCPWM_DITHERING_DUTY&#160;</td><td class="fielddoc"><p>TCPWM dithering is set to duty. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga5ba36f547c6817ce1f2a5ed6e89283ffa38b8de205630c2679848d0fcd1950e70"></a>CY_TCPWM_DITHERING_PERIOD_DUTY&#160;</td><td class="fielddoc"><p>TCPWM dithering is set to period and duty. </p>
</td></tr>
</table>

</div>
</div>
<a id="ga3ba205fa719411684a55b9fc3ad7b79c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3ba205fa719411684a55b9fc3ad7b79c">&#9670;&nbsp;</a></span>cy_en_dithering_limiter_t</h2>

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        <tr>
          <td class="memname">enum <a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga3ba205fa719411684a55b9fc3ad7b79c">cy_en_dithering_limiter_t</a></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TCPWM dithering limiter values. </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79ca2eecdd1341a809c8219db95a13e0a984"></a>CY_TCPWM_DITHERING_LIMITER_1&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 1. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79caa70075b35cc9190d26ccbdd07fe9b68d"></a>CY_TCPWM_DITHERING_LIMITER_2&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 2. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79caa3d2becf221f3824633e559b2d63900b"></a>CY_TCPWM_DITHERING_LIMITER_3&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 3. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79ca4c2b3761444cd8a326e0368d20bd91ee"></a>CY_TCPWM_DITHERING_LIMITER_4&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 4. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79ca875edfba340d2f49fd8ccdb4a3569a96"></a>CY_TCPWM_DITHERING_LIMITER_5&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 5. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79cae10ab73e45c2a8f473563be1f6583730"></a>CY_TCPWM_DITHERING_LIMITER_6&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 6. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga3ba205fa719411684a55b9fc3ad7b79cab050b0e8f57b5721e29183a71dc30abc"></a>CY_TCPWM_DITHERING_LIMITER_7&#160;</td><td class="fielddoc"><p>TCPWM dithering limiter value 7. </p>
</td></tr>
</table>

</div>
</div>
<a id="ga8c9f3eeb107eae3ea2a485f9169e3759"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8c9f3eeb107eae3ea2a485f9169e3759">&#9670;&nbsp;</a></span>cy_en_hrpwm_operating_frequency_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga8c9f3eeb107eae3ea2a485f9169e3759">cy_en_hrpwm_operating_frequency_t</a></td>
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      </table>
</div><div class="memdoc">

<p>HRPWM Operation Frequency Selects the frequency of operation of HRPWM feature. </p>
<p>Micro tick is adjusted based on this information. These bits specifies the frequency of CLK_OUT from TCPWM counter. CLK_OUT = CLK_PERI = CLK_HF </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga8c9f3eeb107eae3ea2a485f9169e3759ad3445cddbdd169c8c23b748651c10ea6"></a>CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ&#160;</td><td class="fielddoc"><p>HRPWM Input Frequency is 80 MHz or 100 MHz. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga8c9f3eeb107eae3ea2a485f9169e3759a6a2af385e701e00ffc26975e7aa52ee5"></a>CY_TCPWM_HRPWM_FREQ_160MHZ_OR_180MHZ&#160;</td><td class="fielddoc"><p>HRPWM Input Frequency is 160 MHz or 180 MHz. </p>
</td></tr>
<tr><td class="fieldname"><a id="gga8c9f3eeb107eae3ea2a485f9169e3759ad646d5983e488f45c84ff63682a09342"></a>CY_TCPWM_HRPWM_FREQ_200MHZ_OR_240MHZ&#160;</td><td class="fielddoc"><p>HRPWM Input Frequency is 200 MHz or 240 MHz. </p>
</td></tr>
</table>

</div>
</div>
<a id="ga19e8127ddd17a33fe06608855cd10c4d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga19e8127ddd17a33fe06608855cd10c4d">&#9670;&nbsp;</a></span>cy_en_kill_line_polarity_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__tcpwm__data__structures__pwm.html#ga19e8127ddd17a33fe06608855cd10c4d">cy_en_kill_line_polarity_t</a></td>
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<p>Specifies the behavior of the PWM outputs line_out and line_out_compl_out while the TCPWM counter is disabled or stopped. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="gga19e8127ddd17a33fe06608855cd10c4da4489e96d5fb2192693ccecd6b3b52251"></a>CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW&#160;</td><td class="fielddoc"><p>Line Out and Line Compl Out is Low during the kill and counter is disabled. </p>
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<tr><td class="fieldname"><a id="gga19e8127ddd17a33fe06608855cd10c4dab544a8708f31372fd8d801493e151cf9"></a>CY_TCPWM_LINEOUT_IS_HIGH_AND_LINECMPOUT_IS_LOW&#160;</td><td class="fielddoc"><p>Line Out is High during the kill and counter is disabled. </p>
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<tr><td class="fieldname"><a id="gga19e8127ddd17a33fe06608855cd10c4da0a02f0fdc317e64177c0d6be7a4d5543"></a>CY_TCPWM_LINECMPOUT_IS_HIGH_LINEOUT_IS_LOW&#160;</td><td class="fielddoc"><p>Line Compl Out is High during the kill and counter is disabled. </p>
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<tr><td class="fieldname"><a id="gga19e8127ddd17a33fe06608855cd10c4da18df07d53c406caef0834c8893814711"></a>CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_HIGH&#160;</td><td class="fielddoc"><p>Line Out and Line Compl Out is Hig during the kill and counter is disabled. </p>
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<h2 class="memtitle"><span class="permalink"><a href="#gab0adb8ee7ffc443e3ce016aec3d447c8">&#9670;&nbsp;</a></span>cy_en_line_select_config_t</h2>

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          <td class="memname">enum <a class="el" href="group__group__tcpwm__data__structures__pwm.html#gab0adb8ee7ffc443e3ce016aec3d447c8">cy_en_line_select_config_t</a></td>
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<p>Source for the output signal "line_out" and "line_compl_out". </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8a6c268b8864615e8ac0ff6086c7d5ad46"></a>CY_TCPWM_OUTPUT_CONSTANT_0&#160;</td><td class="fielddoc"><p>Output signal is 0. </p>
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<tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8a055953ca2ea107432c1c39cf2e60d7cc"></a>CY_TCPWM_OUTPUT_CONSTANT_1&#160;</td><td class="fielddoc"><p>Output signal is 1. </p>
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<tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8ab10a622c4c07bff26bd57271912f71e9"></a>CY_TCPWM_OUTPUT_PWM_SIGNAL&#160;</td><td class="fielddoc"><p>Output signal is PWM Signal. </p>
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<tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8a91dc81f784c9b74718d12e12902e6fe7"></a>CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL&#160;</td><td class="fielddoc"><p>Output signal is inverted PWM Signal. </p>
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<tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8a324edb61b898067f6a5fe5eaa53e2271"></a>CY_TCPWM_OUTPUT_PORT_DEFAULT&#160;</td><td class="fielddoc"><p>Output is not driven by the TCPWM. </p>
<p>Instead the port default level configuration applies, e.g. "Z" (high impedance). </p>
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<tr><td class="fieldname"><a id="ggab0adb8ee7ffc443e3ce016aec3d447c8ad1959ad6cbd6b1978e6037cf0b4ed67e"></a>CY_TCPWM_OUTPUT_SOURCE_MOTIF&#160;</td><td class="fielddoc"><p>Source for PWM signal conditioning comes from MOTIF modulation output control signals. </p>
<p>It can be set to '0' , '1' or PWM. </p>
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